features fast access time : 12/15 ns low power consumption: operating current : 110/100/90/80ma (typ.) standby current : 1ma (typ.) single 5v power supply all inputs and outputs ttl compatible fully static operation tri-state output data retention voltage : 2.0v (min.) green package available package : 28-pin 300 mil soj general description the as7c164 a is a 65,536-bit high speed cmos static random access memory organized as 8,192 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the as7c164 a is well designed for high speed system applications, and particularly well suited for battery back-up nonvolatile memory application. the AS7C164A opera tes from a sin gl e power supp ly of 5v and all inputs and outputs are fully ttl compatible product family power dissipation product family operating temperature vcc range speed standby(i sb1, typ.) operating(icc,typ.) AS7C164A 0 ~ 70 4.5 ~ 5.5v 12/15ns 1ma 110/100/90/80ma f unctional b lock diag ram decoder i/ o data ci rc uit control ci rc uit 8kx8 memor y arr ay co lumn i/o a0-a12 vcc vss dq 0-d q7 ce# we# oe# ce2 pin description symbol description a0 - a12 address inputs dq0 ? dq7 data inputs/outputs ce#, ce2 chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no connection november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 1 of 10 alliance memory inc
pin configuration a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 vss nc vcc a8 a9 a11 a10 dq7 dq6 dq5 dq4 dq3 AS7C164A soj 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 ce2 ce# oe# we# absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 6.5 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v 0 to 70(c grade) t erutarepmet gnitarepo a t erutarepmet egarots stg -65 to 150 p noitapissid rewop d 1 w i tnerruc tuptuo cd out 50 ma *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to the absolute maximum rating conditions for extended period may af fect device reliabi lity. t ru th table mode ce# ce2 oe# we# i/o operation supply current h x x x high-z i sb1 standby x l x x high-z i sb1 output disable l h h h high-z i cc re ad l h l h d out i cc write l h x l d in i cc note: h = v ih , l = v il , x = don't care. november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 2 of 10 alliance memory inc
dc electrical characteristics parameter symbol test condition min. typ. *4 max. unit supply voltage v cc v 5.5 0.5 5.4 input high voltage v ih *1 v - 4.2 cc +0.5 v input low voltage v il *2 v 8.0 - 5.0 - input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss, output disabled - 1 - 1 a output high voltage v oh i oh v - - 4.2 am1- = output low voltage v ol i ol = 2ma - - 0.4 v -12 - 90 160 ma average operating power supply current i cc cycle time = min. ce# = v il and ce2 = v ih , i i/o = 0ma other pins at v ih or v il -15 - 80 140 ma standby power supply current i sb1 ce# v R cc -0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2v - 1 5 ma notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25 cap ac itance (t a = 25 , f = 1.0mhz) parameter symbol min. max unit c ecnaticapac tupni in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions v ot v2.0 slevel eslup tupni cc - 0.2v sn3 semit llaf dna esir tupni input and output timing reference levels 1.5v c daol tuptuo l = 30pf + 1ttl, i oh /i ol = -4ma/8ma november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 3 of 10 alliance memory inc
ac electrical characteristics (1) read cycle parameter sym. read cycle time t rc address access time t aa chip enable access time t ace output enable access time t oe chip enable to output in low-z t clz output enable to output in low-z t olz chip disable to output in high-z t chz output disable to output in high-z t ohz output hold from address change t oh (2) write cycle parameter sym. write cycle time t wc address valid to end of write t aw chip enable to end of write t cw address set-up time t as write pulse width t wp write recovery time t wr data to write time ov erla p t dw data hold from end of write time t dh output active from end of write t ow write to output in high-z t whz *these parameters are guaranteed by device november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 4 of 10 alliance memory inc
timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc prev iou s data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid t oh oe# hig h-z high-z t clz t olz t oe t chz t ohz ce2 t ace ce# t aa address t rc notes : 1.we# is high for read cycle. 2.device is continuous ly selected oe# = lo w, ce# = low ., ce2 = hi gh . 3.a ddress must be valid prior to or coincident with ce# = low , ce2 = high; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 5 00 mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz. november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 5 of 10 alliance memory inc
write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc ce2 notes : 1.we #, ce# must be high or ce2 must be low during all address transitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#. 3.during a we#controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals mu st not be applied. 5.if the ce#low transition and ce2 high transition occurs simultaneously with or after we # low transition, the outputs remain in a high impedance st ate . 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from ste ad y state. november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 6 of 10 alliance memory inc
data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v or ce2 Q 0. 2v 2.0 - 5.5 v data retention current i dr v cc = 2.0v ce# v R cc - 0.2v or ce2 Q 0. 2v others at 0.2 v or v cc -0.2v - 0.6 3 ma chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns re co very time t r t rc * - - ns t rc * = re ad cycle ti me data retention waveform low vcc data retention waveform (1) ( ce# controlled) vcc ce# v dr R 2.0v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vc c( min.) low vcc data retention waveform (2) (ce2 controlled) vcc ce2 v dr R 2. 0v ce2 Q 0.2v vcc(min.) v il t r t cdr v il vc c( min.) november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 7 of 10 alliance memory inc
28-pin 300 mil soj package outline dimension 1 28 14 15 a2 l c xx x note : 1.s/e/d dimension is not including mold flash. 2.the end flash in pack ag e lengthwise is not more than 10 mils ea ch side. unit sym. inch(ref) mm(base) a 0.140 (max) 3.556 (max) a1 0.026 (min) 0.660 (min) a2 0.100 0.005 2.540 0.127 b 0.018 0.003 0.457 0.076 b1 0.028 0.003 0.711 0.076 c 0.010 0.003 0.254 0.076 d 0.710 0.010 18.03 0.254 e 0.337 0.010 8.560 0.254 e1 0.300 0.005 7.620 0.127 e 0.050 0.003 1.270 0.076 l 0.087 0.010 2.210 0.254 s 0.030 0.004 0.762 0.102 y 0.003 (max) 0.076 (max) november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 8 of 10 alliance memory inc
november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 9 of 10 alliance memory inc ordering information part numbering system package/access time temperature 12 ns 15 ns 28-pin 300 mil soj commercial AS7C164A-15jcn AS7C164A-12jcn as7c 164a -xx j c x sram prefix voltage: 5v supply device number access time j = soj, 300 mil temperature range: c = 0 ~ 70 c n = lead free part
november 2009 AS7C164A 8k x 8 bit high speed cmos sram november/2009 v1.2 page 10 of 10 alliance memory inc copyright ? alliance memory all rights reserved alliance memory, inc 551 taylor way, san carlos, ca 94070, usa phone: 650-610-6800 fax: 650-620-9211 www.alliancememory.com ? copyright 2009 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks ofalliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to thisdocument and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the datacontained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at anytime, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inalliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance'sterms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against allclaims arising from such use. ?
|
